Integrated circuits are particularly sensitive to the high voltages encountered as a result of electrostatic discharge (ESD) events, such as may occur when a person touches a lead of an integrated circuit. Prior art silicon-controlled rectifiers (SCRs) have been provided for selectively discharging to ground the high voltages of ESD events Prior to an ESD event, the SCR is in a nonconductive state. Once the high voltage of an ESD event is encountered, the SCR then changes to a conductive state to shunt the current to ground and maintains this conductive state until the voltage is discharged to a safe level.
A problem arises due to the holding voltage of prior art SCRs being lower than the operating voltage at which the protected circuit operates. Thus, a prior art SCR may be triggered by an ESD event or large signal noise and remain latched in a conductive state as long as the operating voltage is applied to the particular circuit being protected. The problem occurs since spurious noise generated when an integrated circuit is operated may activate a sensitive SCR circuit unless, as is currently done in the prior art. This can damage the SCR. Also, the protected circuit cannot be used until the operating voltage is removed from the protected circuit such that the SCR can return to an unlatched, nonconductive state.
A further problem occurs with the reduction in size of integrated circuits, in that the reduced scale of the circuits results in greater sensitivity and susceptibility to damage from ESD events. This is especially true for MOSFET circuits which presently operate at voltage levels of 3.3 volts. MOSFET circuits are easily damaged by ESD events. In order to protect such circuits against ESD events, sensitive SCR circuits must be utilized. Due to the high trigger voltage of an SCR, a resistor must be placed on the signal line being protected. This resistor also adds a time constant, causing a lag in response time of the signal line and distortion of digital signals at high frequencies.